1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating gate electrodes of NMOS and PMOS transistors which may constitute a CMOS semiconductor device.
2. Description of Related Art
A CMOS semiconductor device employs a CMOS transistor circuit composed of an NMOS transistor and a PMOS transistor. The CMOS transistor circuit consumes less power than a semiconductor device composed of a bipolar transistor circuit or an NMOS transistor circuit. For this reason, the CMOS transistor circuit is widely adopted in most semiconductor devices.
Gate electrodes of the NMOS and PMOS transistors of the conventional CMOS transistor circuit are fabricated using a poly-silicon layer doped with n-type impurities. In this case, the PMOS transistor has a buried channel property while the NMOS transistor has a surface channel property. As a result, a short channel effect may deteriorate the leakage current characteristics of the PMOS transistor.
FIGS. 1A through 1C are cross-sectional views illustrating a conventional method of fabricating a dual gate electrode.
Referring to FIG. 1A, a PMOS active region 5P′ and an NMOS active region 5N′ are defined by forming an isolation layer 3 on a semiconductor substrate 1 having PMOS and NMOS transistor regions P′ and N′. A gate insulating layer 9 is formed on the semiconductor substrate 1. A polysilicon layer 11 doped with n-type impurities is formed on the gate insulating layer 9 and then planarized.
Referring FIG. 1B, a photoresist layer pattern 13 exposing the PMOS transistor region P′ is formed on the planarized polysilicon layer 11, and p-type impurities 15 are ion-implanted into the polysilicon layer 11 of the PMOS transistor region P′ using the photoresist layer pattern as an ion implantation mask. Thereafter, the photoresist layer pattern 13 is removed. This influx of p-type impurities offsets the concentration of n-type impurities already implanted in the planarized polysilicon layer 11. As a result, the PMOS and NMOS transistor regions P′ and N′ have a p-type polysilicon layer 11a doped with the p-type impurities 15 and an n-type polysilicon layer 11b doped with the n-type impurities, respectively.
Referring to FIG. 1C, the p-type polysilicon layer 11a and the n-type polysilicon layer 11b are patterned to form an NMOS gate electrode 11N′ in the NMOS transistor region N′ and a PMOS gate electrode 11P′ in the PMOS transistor region P′, respectively.
According to the conventional fabrication method, it is difficult to form the PMOS gate electrode 11P′ and the NMOS gate electrode 11N′ with a high concentration of impurities. This is because if the concentration of n-type impurities is increased in the polysilicon layer 11, it is difficult to increase the concentration of p-type impurities in the PMOS transistor region P′ of the polysilicon layer 11. That is, even if a large dose of p-type impurities are ion-implanted, there is a limit to offsetting the high concentration of n-type impurities already implanted. Also, there is a limit to the concentration of p-type impurities that the polysilicon layer 11 can sustain. As a result, the PMOS and NMOS gate electrodes 11P′ and 11N′ have low concentrations of impurities, which may cause a poly-depletion effect that leads to an increase in the effective thickness of the gate insulating layer and eventual change in a threshold voltage.